Design partially adder using simply nor gate?

relates to digital computer design

Design partially adder using simply nor gate?

A partly adder is a device that has two inputs (A0 and B0), and two outputs (C1 and C0). The inputs are two one-bit binary numbers. The output is the sum of the two inputs, within the form of a two-bit binary number.



The half adder is defined by these equations:

C1 = A0 and B0

C0 = A0 xor B0



It is possible to implement ANY logic function using individual nor gates. So very soon, we have to convert the two equations above into a form that uses solitary nor gates.



You can carry out the conversion by repeatedly applying 4 simple rules. Here they are:

X xor Y = (X and not Y) or (not X and Y)

X nor Y = not ( X or Y )

not X = X nor 0

X or Y = not ( (not X) and (not Y) )



The end result is this:

C1 = (A0 nor 0) nor (B0 nor 0)

C0 = (((A0 nor 0) nor B0) nor (A0 nor (B0 nor 0))) nor 0

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